CMOS Semiconductor Fabrication
CMOS Semiconductor Fabrication

CMOS Semiconductor Fabrication

Tags
Electronics
Research
Project & Writeup Finished
Published
December 12, 2023
Author
Peter Buckley
Status
Completed
Date

Acknowledgments

This report was completed as part of EELE-407 (Microfabrication) at Montana State University, taught by Dr. Kaiser. I’d like to thank Dr. Kaiser as well as the class T.A. for their guidance throughout the course and the MSU Microfabrication Facility for providing the tools and resources that made this project possible.
Figure F1: Final Wafer Produced.
Figure F1: Final Wafer Produced.

Fabrication Theory

Introduction: Silicon microfabrication is a critical process in the semiconductor industry, enabling the creation of intricate microscale structures essential for modern electronic devices. This report highlights the key processes, materials, and common issues involved in silicon microfabrication.
Materials Used: Silicon, renowned for its excellent semiconductor properties, is the primary material in microfabrication. Other materials include metals for conductors, silicon dioxide or nitride for insulators, and doping agents for modifying electrical properties, each chosen for its specific role in the device structure.
Basic Fabrication Techniques:
  1. Photolithography: This process involves applying a light-sensitive photoresist to a silicon wafer, exposing it to UV light through a mask to create patterns, developing the exposed photoresist, and then baking to set the structure.
  1. Etching: Essential for material removal and wafer shaping, etching is performed using chemical solutions (wet etching) or plasma/gases (dry etching), depending on the desired precision and material compatibility.
  1. Deposition: Techniques like Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) are used to deposit thin films of various materials, building up layered structures on the wafer.
  1. Doping/Ion Implantation: Fundamental to silicon microfabrication, this process alters the electrical properties of silicon by introducing doping agents. Ion implantation offers precise control over the doping levels and locations on the wafer.
  1. Oxidation: Thermal oxidation, the process of growing a thin layer of silicon dioxide on the silicon wafer's surface, is crucial for creating insulating barriers and protecting the device.
Process Flow: The integration of these individual processes into a fabrication sequence is intricate and requires careful planning and execution. Each step is conducted in a cleanroom environment to prevent contamination. This is done to maximize yield, or the amount of working devices per wafer.
Conclusion: he importance of silicon microfabrication in the advancement of electronic technology cannot be overstated. Silicon-based electronic components are present in almost all of the common items we use every day, from smartphones and computers to home appliances and automobiles. These components form the backbone of modern digital circuits, enabling the high-speed, efficient, and reliable operation of various electronic devices. The progression of silicon microfabrication has not only transformed the way we communicate, work, and entertain ourselves but has also played a crucial role in the development of critical sectors like healthcare, transportation, and energy.

Fabrication Sequence

My Wafer:
Note: Each Repeated step ie: lithography, oxidation will only be shown once for the first time it is used.
Lab #0 Initial Oxidation
Starting with a blank p-type substrate wafer, we started with a wet oxidation. for minutes. This will grow a layer of silicon dioxide 0.5-1 microns thick. (This process will be shown more in depth for Lab #3)
Figure A1: Lab #0 oxide growth process step. Todd Kaiser EELE407-13.
Figure A1: Lab #0 oxide growth process step. Todd Kaiser EELE407-13.
Lab #1 Photolithography & Etching (N-well)
Lithography
Next we measure the oxide thickness achieved in the previous step. To do this we use the reflectometer. A reflectometer measures the thickness of an oxide layer on a silicon wafer by shining light onto the surface and analyzing the interference pattern of the light reflected from the oxide surface which varies with the film's thickness. My wafer had an average oxide thickness of for this first oxidation.
Figure A2: Lab #1 using reflectometer to measure oxide thickness at 5 points (top, right, bottom, left, and center).
Figure A2: Lab #1 using reflectometer to measure oxide thickness at 5 points (top, right, bottom, left, and center).
Following our oxidation measurements, we then did our first lithography step patterning the n-well. First we cleaned the wafer with di-water and nitrogen, then spun on a positive photoresist liquid.
Figure A3: Lab #1 spinning on positive resist with the spin-coat machine. Wafer is held onto spindle with vacuum where a poker chip size dollop of photoresist is added. The wafer is then spun to evenly distribute photo resist.
Figure A3: Lab #1 spinning on positive resist with the spin-coat machine. Wafer is held onto spindle with vacuum where a poker chip size dollop of photoresist is added. The wafer is then spun to evenly distribute photo resist.
Continuing the lithography process, the wafer is then “soft-baked” to slightly harden the photoresist material for the next step.
Figure A4: Lab #1 wafer being soft baked at  for 1 minute.
Figure A4: Lab #1 wafer being soft baked at for 1 minute.
Now we are ready for the actual lithography. The machine uses a mask and mercury lamp to harden the photoresist. For most lithography steps, you first have to align the mask using the machines integrated microscopes and adjustable platen. But because this is our first lithography, we are creating the alignment marks to use in the future and thus don’t have to align the wafer.
Figure A5: Lab #2 aligning wafer to mask using alignment marks.
Figure A5: Lab #2 aligning wafer to mask using alignment marks.
Finally we develop and hard bake to remove excess photoresist and fully harden remaining photoresist.
Figure A6: Lab #1 developer bath. Wafer is dropped in for 1 minute to remove the uncured photoresist.
Figure A6: Lab #1 developer bath. Wafer is dropped in for 1 minute to remove the uncured photoresist.
Figure A7: Lab #2 wafer being hard baked at  for 1 minute.
Figure A7: Lab #2 wafer being hard baked at for 1 minute.
After this lab we are left with an oxidized wafer with a layer of photo resist masking everything but the n-wells.
Figure A8: Lab #1 N- Well pattern process step. Todd Kaiser, EELE407-13.
Figure A8: Lab #1 N- Well pattern process step. Todd Kaiser, EELE407-13.
Lab #2
Wafer Cleaning Cleaning & Diffusion (N-)
We start by removing oxide windows by soaking the wafers in a buffered oxide etch solution until the bare silicon is shown.
Figure A9: Lab #2 wafers being soaked in BOE solution (I wont include photos of soaking in other solutions as they look the same).
Figure A9: Lab #2 wafers being soaked in BOE solution (I wont include photos of soaking in other solutions as they look the same).
Figure A10: Top window still has some  remaining as seen by the blue color. Bottom window is all etched with bare silicon showing through. CMOS Lab Manual, Matthew Leone & Todd Kaiser.
Figure A10: Top window still has some remaining as seen by the blue color. Bottom window is all etched with bare silicon showing through. CMOS Lab Manual, Matthew Leone & Todd Kaiser.
Now that our windows are etched we can remove the excess photo resist. We can do this in the spin coater by squirting the following onto the wafer while its spinning. Acetone for 10 seconds. Acetone and Isopropanol for 5 seconds. Isopropanol for 5 second. Then let dry for 10.
RCA Clean
Before diffusion, we need to perform an RCA clean. We first soak our wafers in a piranha solution for 10 minutes to remove organics. We then follow with 50:1 BOE for 60 seconds to strip leftover native oxide. Then we finish with an Ionic Clean to remove any heavy metal ions.
Figure A11: Lab #2 removed organics seen as yellow streaks in the solution.
Figure A11: Lab #2 removed organics seen as yellow streaks in the solution.
Figure A12: Lab #2 wafer after BOE etch, photoresist removal, and RCA Clean. Todd Kaiser, EELE407-13.
Figure A12: Lab #2 wafer after BOE etch, photoresist removal, and RCA Clean. Todd Kaiser, EELE407-13.
Diffusion & Drive In
Wafers are then cleaned with di water and inserted into a quartz boat. The wafers are placed 1 slot adjacent to phosphorus disks for diffusion. They are then baked with the phosphorus source at for minutes to populate the substrate with impurities. And baked again without the phosphorus source, at for minutes to drive the impurities into the substrate.
Figure A13: Lab #2 wafers being loaded into quarts boats
Figure A13: Lab #2 wafers being loaded into quarts boats
Figure A14: Lab #2 wafers being inserted into furnace with quarts rod. The wafers are inserted and removed slowly as to keep them from cooling off or heating up to quickly and prevent high stresses from thermal expansion.
Figure A14: Lab #2 wafers being inserted into furnace with quarts rod. The wafers are inserted and removed slowly as to keep them from cooling off or heating up to quickly and prevent high stresses from thermal expansion.
Figure A15: Lab #2 wafer after diffusion and drive in. Blue shows the doped N- well. Todd Kaiser, EELE407-13.
Figure A15: Lab #2 wafer after diffusion and drive in. Blue shows the doped N- well. Todd Kaiser, EELE407-13.
Lab #3 N- Sheet Resistivity & Oxidation
All the remaining oxide is now stripped off with a 6:1 BOE and another RCA clean is done.
Figure A16: Lab #3 wafer after oxide removal. Todd Kaiser, EELE407-13.
Figure A16: Lab #3 wafer after oxide removal. Todd Kaiser, EELE407-13.
4 Point Probe
Now we can measure the sheet resistivity of doped regions. We use to 4 Point Probe to gather this data. This works by running a current across two of the probes. This creates a potential field in the material. Then the other two probes measure the voltage drop. This method minimizes the impact of contact resistance between the probes and the material, which can be significant in 2-point probe measurements.
Figure A17: Lab #3 measuring sheet resistivity of N- Well.
Figure A17: Lab #3 measuring sheet resistivity of N- Well.
After taking measurements we are ready to once again oxidize the wafer to prepare for the patterning of the N+ regions. The wafers are inserted into the wet oxidation furnace at for minutes. Nitrogen and Oxygen gasses are injected into the furnace to induce oxide growth during baking. (Note: oxidation also acts as a further drive in for our deposition)
Oxidation
Figure A17: Lab #3 wafer after 2nd oxidation. Todd Kaiser, EELE407-13.
Figure A17: Lab #3 wafer after 2nd oxidation. Todd Kaiser, EELE407-13.
Lab #4 N+ Lithography & Etch
This process is very similar to our last lithography and etch, with the only differences being the mask used, and the need to align the mask to the alignment marks on the wafer. The N+ regions serve as the source and drain regions for NMOS transistors.
Figure A18: Lab #4 wafer after N+ Lithography. Todd Kaiser, EELE407-13.
Figure A18: Lab #4 wafer after N+ Lithography. Todd Kaiser, EELE407-13.
Figure A18: Lab #4 wafer after N+ windows are etched. Todd Kaiser, EELE407-13.
Figure A18: Lab #4 wafer after N+ windows are etched. Todd Kaiser, EELE407-13.
Figure A19: Lab #4 Top view of N- Well(grey box) and N+ source and drain(white box). Todd Kaiser, EELE407-13.
Figure A19: Lab #4 Top view of N- Well(grey box) and N+ source and drain(white box). Todd Kaiser, EELE407-13.
Lab #5 N+ Diffusion
After doing another RCA clean the wafer is now ready for its N+ deposition. The wafer is baked at for minutes with phosphorus source plates. A drive in is then done at for minutes without the phosphorus plates.
Figure A20: Lab #5 Wafer after N+ deposition and drive in. Todd Kaiser, EELE407-13
Figure A20: Lab #5 Wafer after N+ deposition and drive in. Todd Kaiser, EELE407-13
Lab #6 N+ Sheet Resistivity & Oxidation
The remaining Silicon Dioxide is first etched off with a 6:1 BOE solution and after another RCA clean is done, we measure the sheet resistivity of the N+ region.
Figure A21: Lab #6 Wafer after N+ diffusion and oxide is stripped. Todd Kaiser, EELE407-13
Figure A21: Lab #6 Wafer after N+ diffusion and oxide is stripped. Todd Kaiser, EELE407-13
After this we re-oxidize the wafer at for minutes. (Note: oxidation also acts as a further drive in for our deposition)
Figure A22: Lab #6 Wafer after 3rd oxidation. Todd Kaiser, EELE407-13
Figure A22: Lab #6 Wafer after 3rd oxidation. Todd Kaiser, EELE407-13
Lab #7 P+ Lithography & Etch
This process is very similar to our last lithography and etch, with the only differences being the mask used. The P+ regions serve as the source and drain regions for PMOS transistors.
Figure A23: Lab #7 Wafer after P+ Lithography. Todd Kaiser, EELE407-13
Figure A23: Lab #7 Wafer after P+ Lithography. Todd Kaiser, EELE407-13
Figure A24: Lab #7 Wafer after P+ Windows are etched. Todd Kaiser, EELE407-13
Figure A24: Lab #7 Wafer after P+ Windows are etched. Todd Kaiser, EELE407-13
Figure A25: Lab #7 Top view of P+ Source and Drain(white squares) in the N- Well. Todd Kaiser, EELE407-13
Figure A25: Lab #7 Top view of P+ Source and Drain(white squares) in the N- Well. Todd Kaiser, EELE407-13
Lab #8 P+ Diffusion
After doing another RCA clean the wafer is now ready for its P+ deposition. The wafer is baked at for minutes, this time with boron source plates to achieve a P type substrate. A drive in is then done at for minutes without the boron plates.
Figure A26: Lab #8 Wafer after P+ Diffusion(P+ Source and Drain shown in red). Todd Kaiser, EELE407-13
Figure A26: Lab #8 Wafer after P+ Diffusion(P+ Source and Drain shown in red). Todd Kaiser, EELE407-13
Lab #9 P+ Sheet Resistivity & Oxidation
The remaining Silicon Dioxide is first etched off with a 6:1 BOE solution and after another RCA clean is done, we measure the sheet resistivity of the N+ region.
Figure A27: Lab #9 Wafer after P+ diffusion and oxide is stripped. Todd Kaiser, EELE407-13
Figure A27: Lab #9 Wafer after P+ diffusion and oxide is stripped. Todd Kaiser, EELE407-13
After this we re-oxidize the wafer at for minutes. (Note: oxidation also acts as a further drive in for our deposition)
Figure A28: Lab #9 Wafer after 4rd oxidation. Todd Kaiser, EELE407-13
Figure A28: Lab #9 Wafer after 4rd oxidation. Todd Kaiser, EELE407-13
Lab #10 Gate Oxide Lithography & Etch
This process is very similar to our last lithography and etch, with the only differences being the mask used. The gate oxide serves as a insulating layer between the gate and the channel of transistors.
Figure A29: Lab #10 Wafer after P+ Lithography. Todd Kaiser, EELE407-13
Figure A29: Lab #10 Wafer after P+ Lithography. Todd Kaiser, EELE407-13
Figure A30: Lab #10 Wafer after Gate Oxide Windows are etched. Todd Kaiser, EELE407-13
Figure A30: Lab #10 Wafer after Gate Oxide Windows are etched. Todd Kaiser, EELE407-13
An RCA Clean is then done to remove the remaining photoresist and clean the wafer.
Figure A31: Lab #10 Wafer after excess Gate Oxide photoresist is removed from RCA clean. Todd Kaiser, EELE407-13
Figure A31: Lab #10 Wafer after excess Gate Oxide photoresist is removed from RCA clean. Todd Kaiser, EELE407-13
Figure A32: Lab #10 Top view of Gate Oxide Windows(white squares). Todd Kaiser, EELE407-13
Figure A32: Lab #10 Top view of Gate Oxide Windows(white squares). Todd Kaiser, EELE407-13
Lab #11 Contacts + Vias Lithography & Etch
This process is very similar to our last lithography and etch, with the only differences being the mask used. The metal layer serves as conductors, contacts, and vias for devices.
Figure A33: Lab #11 Wafer after Contacts + Vias Lithography. Todd Kaiser, EELE407-13
Figure A33: Lab #11 Wafer after Contacts + Vias Lithography. Todd Kaiser, EELE407-13
Figure A34: Lab #11 Wafer after Vias are etched. Todd Kaiser, EELE407-13.
Figure A34: Lab #11 Wafer after Vias are etched. Todd Kaiser, EELE407-13.
Physical Vapor Deposition
Now after doing another RCA clean to remove photoresist and clean the wafer, we are ready to use Physical Vapor Deposition to deposit a thin layer of aluminum across the entire wafer. The aluminum evaporation is performed using the MODULAB PVD system. This system likely uses thermal evaporation, where aluminum is heated in a tungsten coil until it vaporizes and then condenses on the cooler wafer surface, forming a thin film of aluminum. Approximately 40-50 cm² of aluminum is evaporated to achieve a film thickness of about 0.5 to 0.7 micrometers on the wafer surface.
Figure A35: Lab #11 Inside of PVD Machine. CMOS Lab Manual, Matthew Leone & Todd Kaiser.
Figure A35: Lab #11 Inside of PVD Machine. CMOS Lab Manual, Matthew Leone & Todd Kaiser.
Figure A36: Lab #11 Metalized Wafer. Todd Kaiser, EELE407-13.
Figure A36: Lab #11 Metalized Wafer. Todd Kaiser, EELE407-13.
Lab #12 Pattern Metal
The aluminum is then patterned, defining the areas where the electrical contact pads are to be formed.
Figure A37: Lab #12 Wafer after metal pattern lithography. Todd Kaiser, EELE407-13.
Figure A37: Lab #12 Wafer after metal pattern lithography. Todd Kaiser, EELE407-13.
The aluminum is then etched with a Phosphoric Acid Etch for 15 minutes. This Acid is highly selective to aluminum, and largely ignores other materials.
Figure A38: Lab #12 Wafer after metal is etched. Todd Kaiser, EELE407-13.
Figure A38: Lab #12 Wafer after metal is etched. Todd Kaiser, EELE407-13.
Figure A39: Lab #12 Top view of finalized metal layers shown in grey. Todd Kaiser, EELE407-13.
Figure A39: Lab #12 Top view of finalized metal layers shown in grey. Todd Kaiser, EELE407-13.
And just like that our wafer is all ready for testing!
Full Process Flow Diagram
Figure A40: Labs 0-12 full process flow diagram. Todd Kaiser, EELE407-13.
Figure A40: Labs 0-12 full process flow diagram. Todd Kaiser, EELE407-13.

Analysis & Measurements

Oxide Calculations & Measurements

To calculate oxidation times we use the following equations and coefficient table.
Coeff Table
<100> Silicon Wet
Linear (B/A)
Parabolic(B)
<111> Silicon Wet
Linear (B/A)
Parabolic(B)
<100> Silicon Dry
Linear (B/A)
Parabolic(B)
<111> Silicon Dry
Linear (B/A)
Parabolic(B)
Lets calculate our first oxidation as an example
Our first oxidization is wet oxidating at for minutes (Our wafers are <100> silicon.
First lets calculate our diffusion coefficients
.
Next lets solve for oxide thickness
Following these same equations I have created a spreadsheet to predict oxide growth for each oxidation process.
Figure B1: Table Oxide Thickness Over Time. Peter Buckley, H02.
Figure B1: Table Oxide Thickness Over Time. Peter Buckley, H02.
notion image
Given these numbers, I plotted the measured and calculated oxide thickness over time.
Figure B2: Chart Oxide Thickness Over Time(Graph Excludes dry oxidation). HO2, Peter Buckley.
Figure B2: Chart Oxide Thickness Over Time(Graph Excludes dry oxidation). HO2, Peter Buckley.
Oxidation Analysis: In our oxidation calculations, we observed that the actual thickness of the oxidized layer on the silicon wafer was about 9.5% thinner on average than our calculated values. This difference, though noticeable, is actually pretty good in the context of our manufacturing process. Typically, slight variations like this are expected due to factors like minor inaccuracies in temperature control during the oxidation process or slight deviations in the silicon wafer's purity and surface conditions. Additionally, the precision of our measuring instruments might not be perfect, contributing to this discrepancy. Overall, achieving such a close match to the theoretical prediction is a positive indication of our experiment's accuracy and the reliability of our methodology.
Figure B3: Wafer profilometer readings showing oxide thickness.
Figure B3: Wafer profilometer readings showing oxide thickness.

Diffusion Calculations & Measurements

To calculate diffusion junction depth we use the following equations and coefficient table.
N-Type: Phosphorus (P) Arsenic (As) Antimony (Sb)
P-Type: Boron (B) Gallium (Ga) Indium (In) Aluminum (Al)
Time in Seconds
= Junction Depth in Cm
Gaussian Diffusion (Infinite Source Drive In)
Erfc Diffusion (Limited Source Pre-deposition)
= Surface Concentration From Irvin Curve
Doping Concentration From p(ohm-cm)
Lets do the calculations of our first deposition as an example. Because we are doing a pre-deposition for the N- Well, we will be doing a N Type Erfc Diffusion.
We are given the following constants.
Figure B4: Diffusion Constants Table.
Figure B4: Diffusion Constants Table.
Now that we have the junction depth, we can use the N Type Erfc Irvin Curve to find our predicted sheet resistivity.
I have created a spreadsheet that goes through this process for each diffusions step.
Figure B5: Diffusion measured and calculated values. HO6, Peter Buckley.
Figure B5: Diffusion measured and calculated values. HO6, Peter Buckley.
Diffusion Analysis: When measuring my diffusion sheet resistivity, I observed a substantial discrepancy's between my calculated and measured values, which were 37.9% to 95.77% lower. I believe this variation is primarily attributed to inaccuracies in my initial calculations or constants, not as a result of the wafer processing itself. This is because my measured sheet resistivity values aligned closely with those of my classmates, therefore the error between measured and calculated values is most likely attributed to incorrect calculated values rather than inaccuracy's or mistakes in the microfabrication process.
Figure B6: MATLAB Graph of Wafer Surface Concentration. HO6, Peter Buckley.
Figure B6: MATLAB Graph of Wafer Surface Concentration. HO6, Peter Buckley.

PVD Calculations

Physical Vapor Deposition (PVD) is a vacuum coating process used to deposit thin films of material onto silicon wafers. In PVD, the material to be deposited (usually a metal) is physically transferred from a source to the substrate in a vacuum chamber. The process typically involves either evaporating the source material and then condensing it on the substrate, or sputtering, where atoms are ejected from the source material by high-energy particle bombardment and then deposited on the substrate. PVD allows for the creation of thin, uniform coatings, and is widely used in semiconductor manufacturing for depositing metal layers.
Here is an example problem calculating PVD time.
A silicon wafer sits on a bench in the laboratory at a temperature of 300K and a pressure of 1 atm. Assume that the air consists of 100% oxygen. How long does it take to deposit one atomic layer of oxygen on the wafer surface, assuming 100% adhesion.
Values from textbook
Figure B7: Wafer profilometer readings showing metal layer thickness.
Figure B7: Wafer profilometer readings showing metal layer thickness.

Device Testing

Resistors

In our semiconductor fabrication project, we concentrated on producing four specific resistor types on our silicon wafers, each with its own electrical properties. These were the P-Plus, N-Plus, Metal, and Tub resistors. To explore different performance characteristics, we fabricated these resistors in four varying sizes: 1300x30, 2340x30, 4700x30, and 8820x30. Each resistor type was created in all four sizes. Below, you'll find images of the P+ and N+ resistors. Unfortunately, I didn't take pictures of the metal and tub resistors, but they look quite similar to the ones shown.
Figure C1: Picture of P-Plus resistor bank.
Figure C1: Picture of P-Plus resistor bank.
Figure C2: Picture of N-Plus resistor bank.
Figure C2: Picture of N-Plus resistor bank.
To compare the differing electrical characteristics of each type of resistor, I will be looking at the graphs of the 2340x30 resistors. But first, the probes have an inherent resistance, along with a contact resistance, which we need to take into account in order to take accurate measurements. To measure this we place both probes on a single pad and take a measurement. For me this value was .
Figure C3: 2340x30 Metal resistor testing graph.
Figure C3: 2340x30 Metal resistor testing graph.
Figure C4: 2340x30 N+ resistor testing graph.
Figure C4: 2340x30 N+ resistor testing graph.
Figure C5: 2340x30 P+ resistor testing graph.
Figure C5: 2340x30 P+ resistor testing graph.
Figure C6: 2340x30 Tub(N-) resistor testing graph.
Figure C6: 2340x30 Tub(N-) resistor testing graph.
Figure C7: Average measured 4 point probe values for each resistor material.
Figure C7: Average measured 4 point probe values for each resistor material.
Figure C8: Metal resistor measured vs expected values table.
Figure C8: Metal resistor measured vs expected values table.
Figure C9: N+ resistor measured vs expected values table.
Figure C9: N+ resistor measured vs expected values table.
Figure C10: P+ resistor measured vs expected values table.
Figure C10: P+ resistor measured vs expected values table.
Figure C11: Tub(N-) resistor measured vs expected values table.
Figure C11: Tub(N-) resistor measured vs expected values table.
  1. Metal Resistor Analysis: The graph C3 for the metal resistor shows a straight line that passes through the origin (0,0) with a relatively gentle slope. This straight line is a classic sign of ohmic behavior, which is common in metals and suggests that the resistor maintains a consistent, low resistance over different voltages. Metals are known for their efficient electrical conductivity, which explains their lower resistance. According to the data in table C8, the resistance of the metal resistor was only off by 31.19% to 69.41% from the calculated values, which is quite accurate compared to my other resistors. The small differences observed might be due to several reasons, such as variations in the thickness of the metal, differences in contact resistance, or potential errors in the 4 point probe measurements.
  1. N+ Resistor Analysis: The graph C4 for the N+ resistor shows a noticeable non-linearity, passing through 0,0 but with a pronounced steep slope. This non-linear behavior likely results from the high doping levels used, which can introduce complex charge carrier dynamics, leading to variable resistance under different applied voltages. It demonstrates higher resistance than the metal resistor, a common characteristic in heavily doped semiconductor materials. According to the data in table C9, the resistance of the N+ resistor was found to be off by multiple magnitudes from the calculated values, indicating a significant disparity. The extreme differences observed might be due to several reasons, including error in calculation, 4 point probing the wrong location on the wafer, or inaccuracies in the measurement technique. Errors in the N+ diffusion step such as driving in the impurities too far or contamination of the wafer could also be the cause
  1. P+ Resistor Analysis: Graph C5 for the P+ resistor is linear, similar to the metal resistor, but with a slightly steeper slope, indicating greater resistance. The linearity suggests purely resistive electrical behavior, which is a desirable attribute in most circuit applications. Excluding the 8820x30 resistor, whose resistance of of range, the error in table C10 is very reasonable ranging from 19.65%-35.3%. These small discrepancies could be due to a various factors such as over or under diffusion, differences in contact resistance, or potential errors in the 4 point probe measurements.
  1. N-(Tub) Resistor Analysis: The graph C6, representing the Tub(N-) resistors, exhibits a distinctly non-linear pattern and fails to intersect the origin, implying that a certain threshold voltage is required for current conduction. This behavior might be attributed to lower doping concentrations or the influence of electromagnetic interference. The graph's steep slope points to a high resistance, typical for lightly doped materials. Upon examining table C11, additional inconsistencies become apparent, with the resistors displaying a significantly high deviation from the calculated values. Intriguingly, the resistance tends to decrease as the length of the resistor increases, which is an unusual trend. These anomalies could stem from a variety of sources, such as inconsistencies in the doping process, variations in the material properties, or potential errors in the measurement techniques. Environmental factors during testing or uneven distribution of dopants along the length of the resistors could also contribute to these irregularities.

Diodes

Figure C12: Picture of wafer 1 & 2 Diffusion Diodes.
Figure C12: Picture of wafer 1 & 2 Diffusion Diodes.
Figure C13: 1 Diffusion Diode forward current.
Figure C13: 1 Diffusion Diode forward current.
Figure C14: 1 Diffusion Diode reverse current.
Figure C14: 1 Diffusion Diode reverse current.
Figure C15: 2 Diffusion Diode forward current.
Figure C15: 2 Diffusion Diode forward current.
Figure C16: 2 Diffusion Diode reverse current.
Figure C16: 2 Diffusion Diode reverse current.
Diode Analysis: Both single and double diffusion diodes exhibit nearly the exact same behaviors when provided with a forward and reverse I-V Sweep. This indicates a high level of consistency in the fabrication process and the fundamental operational principles of these diodes. Such uniformity in response, regardless of the diffusion method used, suggests that both types of diodes are well-optimized for their intended functions. This uniform behavior in I-V characteristics is a positive indication of the reliability and repeatability of the manufacturing process, which is essential in semiconductor production.
The turn on voltage of the double diffusion diode is also only compared to the single diffusion turn on voltage of Both curves flatten out at The only other visible differences between the single and double diffusion diodes is that the double diffusion diode exhibits a much more linear I-V curve. This linearity is advantageous in many situations because it allows for more predictable and stable performance, especially in precision electronic applications.

Transistors

Figure C17: Picture of wafer N Type Transistors.
Figure C17: Picture of wafer N Type Transistors.
Smallest Working NMOS 30x40
Figure C18: 30x40 NMOS Transistor, gate voltages from bottom to top = -5, 0, 5, 10, 15.
Figure C18: 30x40 NMOS Transistor, gate voltages from bottom to top = -5, 0, 5, 10, 15.
Smallest NMOS Almost Functional
Figure C19: 10x40 NMOS Transistor, gate voltages from bottom to top = -5, 0, 5, 10, 15.
Figure C19: 10x40 NMOS Transistor, gate voltages from bottom to top = -5, 0, 5, 10, 15.
NMOS Analysis: After testing all my devices in two different transistor banks, I discovered Figure C18 30x40 to be my smallest working transistor size. Figure C19 a 10x40 resistor also seemed to be operational but exhibited some non-ideal behavior at high drain voltages.
The 10x40 transistors appear to exhibit drain-induced barrier lowering (DIBL), a phenomenon typically caused by short-channel effects in small transistors. DIBL is the result of the electric field from the drain end extending into the channel and lowering the potential barrier at the source end making it easier for electrons to flow from the source to the drain, leading to a deviation from the ideal behavior. This effect becomes more pronounced at high drain voltages, as observed in the 10x40 transistors, and manifests as exponential increases in current, evident in the curve shapes at the end of the graph.
 
Figure C20: Picture of wafer P Type Transistors.
Figure C20: Picture of wafer P Type Transistors.
Figure C21: 10x40 NMOS Transistor, gate voltages from bottom to top = -5, 0, 5, 10, 15 (all 5 lines are directly on top of each other for this one).
Figure C21: 10x40 NMOS Transistor, gate voltages from bottom to top = -5, 0, 5, 10, 15 (all 5 lines are directly on top of each other for this one).
PMOS Analysis: During extensive testing of my largest devices across four different transistor banks, I encountered an unexpected issue - none of the PMOS transistors appeared to be functioning correctly. Instead of displaying the characteristic curves of a working PMOS transistor, all the I-V curves I measured showed behavior resembling that of diodes, regardless of the gate voltages applied.
This diode-like behavior could suggest a few underlying issues in the PMOS transistors.
One possible explanation for this phenomenon is the occurrence of a short circuit between the source and the drain regions of the transistors. In a typical PMOS operation, varying the gate voltage should modulate the current flow between these two terminals. However, if there's an unintended short between them, the transistor would behave more like a diode, allowing current to flow in one direction regardless of gate voltage.
Another potential cause could be an issue with the gate oxide layer. If the gate oxide is damaged or too thin, it might not effectively control the channel formation, leading to unregulated current flow similar to a diode.

Conclusion

The microfabrication lab experience offered a comprehensive insight into the complexities of semiconductor device fabrication, with a focus on transistors and diodes. This journey has been both challenging and illuminating, providing a practical understanding of the fabrication and analysis of these essential electronic components.
The diode fabrication part of the lab was particularly successful. The I-V characteristics of the diodes closely aligned with theoretical models, indicating precise control over the p-n junction formation and the effectiveness of our doping and photolithography techniques.
In our exploration of transistors, we focused on NMOS and PMOS devices. While the NMOS transistors provided valuable insights, particularly regarding scaling effects and short-channel phenomena, our work with PMOS transistors presented an intriguing anomaly: they exhibited diode-like behavior. This unexpected result was primarily due to issues in the fabrication process. Specifically, it's likely that the p-n junctions in the PMOS transistors were not properly isolated, leading to a direct path for current flow similar to a diode. This could have been caused by over-diffusion or under-etching, which resulted in the formation of unintended p-n junctions. It highlights the delicate balance required in doping concentrations and the precision needed in etching processes to correctly form transistor structures.
These challenges with PMOS transistors underscore the need for meticulous process control in semiconductor manufacturing. The sensitivity of these devices to slight variations in fabrication parameters became evident, emphasizing the importance of uniformity and precision in every step of the process.
Overall, the lab experience was invaluable, deepening our understanding of semiconductor physics and device fabrication. The successes in diode and NMOS transistor fabrication, coupled with the learning opportunities presented by the PMOS transistors, have significantly enhanced our appreciation for the intricacies of microfabrication. This knowledge is crucial for anyone aspiring to work in the semiconductor industry or engage in further academic research in this field.